Since the invention of transistors in 1947, silicon (Si)-based semiconductor technology has dramatically boosted the development of the information age via continuous device miniaturization. With the channel scale of transistors approaching less than 10 nm, the notorious short-channel effects seriously hinder the realization of a high integration level with low power consumption in a single chip. The exploration of novel materials as well as device structures is extremely urgent to break through Moore’s law and thus extend the scaling limit for high-performance electronics. The emergence of two-dimensional (2D) layered materials with the atomically thin nature provides a great opportunity to overcome the bottlenecks in Si-based complementary metal oxide semiconductor (CMOS) devices (e.g. short-channel effects), which have been regarded as among the promising building blocks for next-generation nanoelectronics.
Although 2D material-based nanodevices have been extensively investigated and exhibit highly competitive performance compared with their conventional bulk semiconductor counterparts, there are great challenges to be surmounted before practical applications can be realized. The "contact" between semiconductors and metal electrodes is one of the key factors in 2D devices, which governs the charge carrier injection from metal to 2D channel. The energy level alignments (ELAs) at the 2D/metal interface play a dominant role in determining the Schottky barrier (SB) that leads to nonnegligible contact resistance and thus limits device performance. For example, a large SB or contact resistance can significantly deteriorate the performance of a 2D FET, such as current on/off ratio, field-effect mobility, and subthreshold swing (SS). Therefore, it is crucial to develop effective contact engineering approaches to form ohmic contacts in 2D devices.
Figure1. Growing Al2O3 on graphene treated by H2 plasma(a). Schematic fabrication process of the edge contact (b, c). The silicon carbide (SiC)-graphene- Al2O3 heterostructure is patterned by EBL and RIE to expose the graphene edge(b). Deposition of Cr (20 nm) and Au (10 nm) to form edge contact(c). SEM image showing the details of the edge-contact structure (the bean-like materials are those leftover of photoresist) (d).
Figure2 . Optical image of a TLM device with edge-contacts (a), and field effect transistor (FET) (b).Total resistance versus channel length, tested graphene device made in TLM geometry with side contacts(a, c). Inset shows the enlarged view of the intercept. Transfer characteristics at VDS = 1V for the device using top gate shown in (d).Inset shows an enlarged view of the Dirac point.
